The present invention is related generally to the field of nonvolatile memory that is made up of an array of memory cells and, more particularly, to a method and apparatus at least for initiating error compensation for such memory responsive to a quality monitor.
A recent trend relating to flash memory resides in attempting to increase storage capacity by increasing the amount of information that is stored by individual memory cells which collectively make up an array of memory cells. As recognized, for example, by U.S. Published Patent Application no. 2008/0162791 (hereinafter, the '791 Application), which is incorporated herein by reference, increasing the number of data levels per memory cell causes a proportionally increasing probability of error when data is read back from the memory. This increase in error probability is attributable, at least in part, to increasing the number of data levels stored by each memory cell since an associated increase in accuracy would be needed to resolve between the data levels. Hence, it is more likely that distortion mechanisms, which affect the values stored by the individual memory cells, can contribute a shift in a data value stored by a given memory cell that can result in improperly shifting a read data value across a threshold between the relatively more closely positioned data thresholds. The '791 Application teaches the use of error correction codes to compensate for the increase in error probability. While the '791 Application represents a remarkable improvement over the then-existing state-of-the-art, Applicants, believe that additional techniques can be employed which provide sweeping improvements over the '791 Application.
In addition to the exemplary aspects and embodiments described above, further aspects and embodiments will become apparent by reference to the drawings and by study of the following descriptions.